Speaker
Cesar Gonzalez Renteria
(Lawrence Berkeley National Laboratory)
Description
The readout circuit (RD53B) for the pixel detector is a joint effort by both the ALTAS and CMS experiments by the RD53 collaboration.
In this talk I will give the status of the RD53 collaboration work on the design and verification
of RD53B. Using 65nm technology and spanning a 384x400 pixel matrix expecting a maximum hit-rate of 3 GHz/cm2, this chip
is the most complex ASIC designed for particle colliders.
With 22 collaborating institutes, a solid verification framework is essential in the proper testing
of the chip design and ensuring the success of the project.
Verification Engineering, as a means of testing the design of an integrated circuit before
it is sent to be fabricated en masse, is considered a critical part of the design life cycle.
Verification is used to identify and eliminate serious bugs in a design that can lead to
increase in cost of the design process as well as delaying significantly design submission
and physical testing. To this end the Universal Verification Method (UVM) created to be used by
all major Electrid Design Automation (EDA) companies is implemented to measure the chip design
meets specification. This spans from writing tests to probe digital logic to simulating power
consumption at the per chip level.
Primary author
Cesar Gonzalez Renteria
(Lawrence Berkeley National Laboratory)
