Introduction to FPGA and its architecture
FPGA: Parallelism in program execution
FPGA: Clock Frequency, Latency, Pipelining
Introduction to Vivado HLS, Setup
Hands-on with Xilinx's Vivada HLS, review synthesis output
Hands-on with Vivada HLS, Introduction to Pragmas (Array_map, Array_partition, Unroll)
HLS Pragmas: Allocation, Latency, Resource, Dataflow, Stable, Inline, Pipeline, Array_map, Array_partition)
HLS Pragma's effect on performance
HLS Pragmas: Loop_flatten, Loop_merge & Some good practices
Recommended HLS coding styles
LHC, CMS Level-1 Trigger, Project
Project: Re-designing RCT
Introduction to VHDL
Introduction to VHDL-contd...